The semiconductor industry has moved to using copper for various aspects of forming a semiconductor device due to certain advantages of copper over other metals. Copper has a first advantage of having a lower resistivity over, for example aluminum, which contributes to lower resistance-capacitance delays which allows a device to operate at faster speeds. Copper further has a higher electromigration resistance which permits smaller scaling of semiconductor devices. However, as the semiconductor industry moves towards copper, certain problems particular to copper arise. One such problem is that copper has a high diffusivity through dielectric and silicon materials on which the copper is deposited which may cause poisoning of the materials and semiconductor device failure.
To correct the diffusivity issue, a barrier material must typically be deposited between the copper layer and the dielectric material to prevent the copper from diffusing into the dielectric or silicon material. Typically, titanium nitride has been used as a barrier material for metals such as aluminum, but titanium nitride has not been as effective for copper. Instead, tantalum based barrier materials have been used with copper. However, tantalum has further problems in that tantalum, and even tantalum nitride, is not amorphous and therefore has porous boundaries which create a diffusion path. Tantalum silicon nitride (TaSiN) is a superior barrier material for copper in semiconductor devices due to its amorphous nature and consequently superior barrier properties towards preventing copper diffusion.
However, the deposition of TaSiN as a barrier material poses other problems. TaSiN is typically deposited using physical vapor deposition (PVD), rather than chemical vapor deposition (CVD), since CVD of TaSiN is more expensive and, due to the non-availability of suitable precursors, presents practical difficulties in its implementation. In PVD, a target material containing tantalum silicon is sputtered using reactive ion sputtering (RIS) in a nitrogen containing plasma to form the TaSiN film. This technique, however, causes enrichment of silicon in undesirable locations of the barrier material. Specifically, as shown in prior art FIG. 1, using PVD with TaSiN causes enrichment of silicon (represented as silicon 12) at the trench bottom 15 of the trench 10 due to differences in sticking coefficients of the tantalum rich and silicon rich species that have been sputtered off a target and also due to preferential re-sputtering of silicon from the surface of the film deposited onto the substrate 21. The resputtering effect is weakest within the etched geometries. Both these effects contribute to the enrichment of silicon at the trench bottom 15. With silicon enrichment occurring at the trench bottom 15, the contact resistance at the interface 20 between the trench and the substrate 21 may become unacceptably high causing device failure. A need therefore exists for a method of forming the barrier material, that is TaSiN, into a trench to have a uniform thickness and no silicon enrichment at the bottom of the trench that may cause device failure.
Related to this need for forming a barrier material to avoid silicon enrichment and create a uniform thickness is the need to ensure that such a barrier material may be used with lower dielectric constant (low K) materials. For example, from prior art FIG. 1, there are advantages to using a dielectric material 22 having a low K. Low K materials are increasingly being used as dielectric material between metallic interconnects and integrated circuits due to advantages realized in minimizing RC delay. When used in conjunction with copper metallization, the above benefits are maximized due to the low electrical resistivity of copper when compared with aluminum based metallizations. However, a problem exists with using the low K material in typical PVD processes in that the adhesion of barrier materials to low K dielectrics is poor due to the combination of high intrinsic stress of barrier materials and damage to the low K material during the deposition which lowers its cohesive strength. CVD barrier materials are typically deposited at higher temperatures which render the low K material unstable. As such, a need exists for combining both copper and low K materials in a semiconductor device without overheating or damaging the low K material.
A technique exists for depositing a film using inductively coupled plasma (ICP) PVD that involves the use of an apparatus as shown in prior art FIG. 2. The general technique is described in U.S. Pat. No. 5,178,739 assigned to International Business Machines and incorporated herein by reference. In ICP PVD, a target 25 and a substrate 30 are within a vacuum chamber 35. Using a sputtering source such as a magnetron source (not shown) outside of the chamber behind target 25, atoms are sputtered off the target. Radio Frequency (RF) power 50 is inductively coupled to RF coils 55 into the chamber to maintain the plasma region 45 which serves to ionize the sputtered tantalum and silicon rich species. The substrate 30 is attached to a bias RF power 60 to control ion direction and energy. In operation, the RF power 50 is applied through the coils 55 to ionize the sputtered atoms in the plasma region 45. The bias RF power 60 is coupled to the substrate 30 to develop a negative bias so that the ionized atoms are accelerated into features etched in the substrate 30 to form a film of a barrier material. Deposition is done at a relatively high chamber pressure compared to a standard PVD technique.
The Applicants have recognized a need to develop a copper barrier layer using TaSiN and the ICP PVD technique to avoid the problems discussed above. Specifically, the need exists for a method of forming a semiconductor device with a copper barrier layer having a uniform thickness, avoiding silicon enrichment at the bottom of trenches and that is compatible with low K dielectrics.